The use of metal foil substrates (e.g., stainless steel, aluminum, copper, etc.) in the construction of semiconductor devices enables the fabrication of semiconductor products that can be flexible. In addition, the use of metal foil substrates allows for high temperature processing of electrical device layers, features and/or devices formed thereon, without significant degradation of the properties of the metal foil substrate. However, at elevated temperatures, components of a metal foil substrate (e.g., in the case of a stainless steel substrate, atoms of iron and/or of an alloying element such as chromium, nickel, molybdenum, niobium, etc.) may have a high enough diffusivity that they may diffuse from the metal foil substrate into one or more electrical device (e.g., semiconductor or dielectric) layer(s), feature(s) and/or device(s) formed thereon, thereby compromising its electrical properties.
For example, referring to FIG. 1, an exemplary semiconductor device, thin-film transistor (TFT) 5, is shown. An insulating layer 20 lies between metal foil substrate 10 and semiconductor body 30. Semiconductor body 30 has source/drain regions 60 and 70 formed therein, and a gate stack comprising gate dielectric 40 and gate electrode 50 formed thereon. During an annealing step, TFT 5 on substrate 10 may be heated to a temperature sufficient to activate a dopant in source/drain regions 60 and 70 and/or at least partially crystallize semiconductor body 30. Such elevated temperatures (e.g., >350° C., and particularly >600° C.) may increase the mobility of metal atoms in the metal foil substrate 10 sufficiently to enable the diffusion lengths of the metal atoms to be comparable to the insulator thickness. Diffusion of metal atoms from substrate 10, through insulator layer 20, as shown by arrows 80, into the active region(s) of TFT 5 (e.g., a channel region of semiconductor body 30 and/or source/drain regions 60 and 70) and/or gate dielectric region 40 may degrade the operating characteristics of TFT 5 (e.g., the threshold voltage, subthreshold slope, leakage current and/or on-current of TFT 30). Therefore, it is desirable to provide a diffusion barrier between metal substrate 10 and semiconductor layer 30 (or other device layer) formed thereon, to prevent such diffusion of metal atoms from substrate 10, through insulator layer 20, into the active region of TFT 5 and/or into gate dielectric region 40 thereover. It is also desirable to provide a diffusion barrier between metal substrate 10 and any device layer thereover in other devices, such as capacitors, diodes, inductors, resistors, etc., where the addition of metal atoms may cause an undesirable change in properties of the device layer.